DFT focus on strategy definition through logic design and insertion, pre-silicon verification, pattern generation, and ATE bringup for NVIDIA chips, with special emphasis on ATE bringup, pattern/generation and validation, yield debug, failure analysis and volume diagnosis for ramp to production.

As a DFT intern at NVIDIA, you will help own the testing methodology from strategy definition through logic design and insertion, pre-silicon verification, pattern generation, and ATE bringup.

What you’ll be doing:

• DFT logic implementation and verification

• Maintain DFT flow and run regression

• Run DFT verification

• Pattern generation and bringup

What we need to see:

• Strong logic design and verification background

• Possess very basic knowledge of DFT

• Skilled in Perl/tcl programming

• Proficient at Verilog HDL

• MS/PhD in EE

Ways to stand out from the crowd:

• Prefer to have experience with logic simulators and debug tools (such as vcs, ncsim, verdi)

• Familiar with C/C , Makefile is a plus

• Strong problem solving and analytical skills

• Excellent communication skills and teamwork

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